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Integrated Circuit Systems, Inc.
ICS9148-12
Frequency Timing Generator for Pentium/ProTM or TransmetaTM EfficeonTM
General Description
ICS9148-12 is a Clock Synthesizer chip for Pentium/Probased Desktop/Notebook systems or Transmeta Efficeon Mobile systems. Features include four strong CPU, seven PCI and eight SDRAM clocks. Two reference outputs are available equal to the crystal frequency. Stronger drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. This device meets rise and fall requirements with 2 loads per CPU output (ie, one clock to CPU and NB chipset, one clock to two L2 cache inputs). PWR_DWN# pin allows low power mode by stopping crystal OSC and PLL stages. For optional power management, CPU_STOP# can stop CPU (0:3) clocks and PCI_STOP# will stop PCICLK (0:5) clocks. CPU and IOAPIC output buffer strength controlled by CPU 3.3_2.5# pin to match VDDL voltage. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 505% duty cycle. The REF clock outputs typically provide better than 0.5V/ ns slew rates. The ICS9148-12 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.
Features
* * * * * * * * * * * * * * CPU outputs are stronger drive for multiple loads per pin (ie CPU and NB on one pin) Generates system clocks for CPU, IOAPIC, SDRAM, PCI, plus 14.314 MHz REF(0:1), USB, Plus Super I/O Supports single or dual processor systems I2C serial configuration interface provides output clock disabling and other functions MODE input pin selects optional power management input control pins Two fixed outputs separately selectable as 24 or 48MHz Separate 2.5V and 3.3V supply pins 2.5V or 3.3V outputs: CPU, IOAPIC 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz CPU 3.3_2.5# logic pin to adjust output strength No power supply sequence requirements Uses external 14.318MHz crystal 48 pin 300 mil SSOP and 240 mil TSSOP Output enable register for serial port control: 1 = enable 0 = disable
Pin Configuration
Block Diagram
48-Pin SSOP & TSSOP
Functionality
VDD (1:4) 3.3V10%, VDDL1, 2 2.55% or 3.310% 0-70C Crystal (X1, X2) = 14.31818 MHz
SEL 0
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CPUCLK, SDRAM (MHz) 60 66.6
PCICLK (MHz) 30 33.3
1
Transmeta and Efficeon are trademarks of Transmeta Corporation. Pentium/Pro is a trademark of Intel Corporation.
ICS9148-12
Pin Descriptions
PIN NUMBER 2, 1 3, 10, 17, 24, 31, 37, 43 4 5 6 7, 15 8 9, 11, 12, 13, 14, 16 18 19 20 21 22 23 25 26 PIN NAME REF (0:1) GND X1 X2 MODE VDD2 PCICLK_F PCICLK (0:5) SEL66/60# SDATA SCLK VDD4 48/24MHzA 48/24MHzB VDD SDRAM7 PCI_STOP# SDRAM6 CPU_STOP# VDD3 VDDL2 CPUCLK (0:3) SDRAM (0:5) PWR_DWN# IOAPIC VDDL1 CPU3.3-2.5# VDD1 TYPE OUT PWR IN OUT IN PWR OUT OUT IN IN IN PWR OUT OUT PWR OUT IN OUT IN PWR PWR OUT OUT IN OUT PWR IN PWR DESCRIPTION Reference clock Output Ground (common) Cr ystal or reference input, has internal cr ystal load cap Cr ystal output, has internal load cap and feedback resistor to X1 Input function selection Supply for PCICLK_F, PCICLK (0:5), nominal 3.3V Free running PCI clock, not affected by PCI_STOP# PCI clocks Selects 60MHz or 66.6MHz for SDRAM and CPU I2C data input I2C clock input Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V 48/24MHz driver output for USB or Super I/O 48/24MHz driver output for USB or Super I/O Supply for PLL core, nominal 3.3V SDRAM clock 60/66.6MHz (selected) Halts PCI Bus (0:5) at logic "0" level when low SDRAM clock 60/66.6MHz (selected) Halts CPU clocks at logic "0" level when low Supply for SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, nominal 3.3V Supply for CPUCLK (0:3), either 2.5 or 3.3V nominal CPUCLK clock output, powered by VDDL2 SDRAMs clock at 60 or 66.6MHz (selected) Powers down chip, active low IOAPIC clock output, (14.318MHz) powered by VDDL1 Supply for IOAPIC, either 2.5 or 3.3V nominal 3.3 or 2.5 VDD buffer strength selection, has pullup to VDD, nominal 30K resistor. Supply for REF (0:1), X1, X2, nominal 3.3V
27 28, 34 40 42, 41, 39, 38 36, 35, 33, 32, 30, 29 44 45 46 47 48
Power Groups
VDD = Supply for PLL core VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP# VDD4 = 48/24MHzA, 48/24MHzB VDDL1 = IOAPIC VDDL2 = CPUCLK (0:3)
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ICS9148-12
Power-On Conditions
SEL 66/60# MODE PIN # 38, 39, 41, 42 36, 35, 33, 32, 30, 29, 27, 26 16, 14, 13, 12, 11, 9, 8 38, 39, 41, 42 36, 35, 33, 32, 30, 29, 27, 26 16, 14, 13, 12, 11, 9, 8 26 27 8 1 0 38, 39, 41, 42 36, 35, 33, 32, 30, 29 16, 14, 13, 12, 11, 9 26 27 8 0 0 38, 39, 41, 42 36, 35, 33, 32, 30, 29 16, 14, 13, 12, 11, 9 CPUCLKs SDRAM PCICLKs CPUCLKs SDRAM PCICLKs PCI_STOP# CPU_STOP# PCICLK_F DESCRIPTION CPUCLKs SDRAM PCICLKs CPUCLKs SDRAM PCICLKs PCI_STOP# CPU_STOP# PCICLK_F FUNCTION 66.6 MHz - w/serial config enable/disable 66.6 MHz - All SDRAM outputs 33.3 MHz - w/serial config enable/disable 60 MHz - w/serial config enable/disable 60 MHz - w/serial config enable/disable 30 MHz - w/serial config enable/disable Power Management, PCI (0:5) Clocks Stopped when low Power Management, CPU (0:5) Clocks Stopped when low 33.3 MHz - 33.3 MHz - PCI Clock Free running for Power Management 66.6 MHz - CPU Clocks w/exter nal Stop Control and serial config individual enable/disable. 66.6 MHz - SDRAM Clocks w/serial config individual enable/disable. 33.3 MHz - PCI Clocks w/exter nal Stop control and serial config individual enable/disable. Power Management, PCI (0:5) Clocks Stopped when low Power Management, CPU (0:5) Clocks Stopped when low 30 MHz - PCI Clock Free running for Power Management 60 MHz - CPU Clocks w/exter nal Stop control and serial config individual enable/disable. 60 MHz - SDRAM Clocks w/serial config individual enable/disable. 30 MHz - PCI Clocks w/exter nal Stop control and serial config individual enable/disable.
1
1
0
1
Example: a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively. b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and "on" condition. The frequencies that are then produced are on the MODE pin as shown in the table below.
CLOCK REF (0:1) I OA P I C 0 48/24 MHz
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D E FAU LT C O N D I T I O N AT P OW E R - U P 14.31818 MHz 14.31818 MHz 48 MHz
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ICS9148-12
Technical Pin Function Descriptions
VDD(1,2,3,4) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B and SDRAM(0:7). This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. VDDL1,2 This is the power supplies for the CPUCLK and IOAPCI output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. See the data tables for the value of this capacitor. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is connected to ground. See the Data Sheet for the value of this capacitor. CPUCLK (0:3) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks are controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. SDRAM(0:7) These Output Clocks are use to drive Dynamic RAM's and are low skew copies of the CPU Clocks. The voltage swing of the SDRAM's output is controlled by the supply voltage that is applied to VDD3 of the device, operates at 3.3 volts. 48/24MHzA, B This is a fixed frequency Clock output that is typically used to drive Super I/O devices. Outputs A and B are defined as 24 or 48MHz by I2C register (see table). IOAPIC This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or 3.3volts. REF(0:1) The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. PCICLK_F This Output is equal to PCICLK(0:5) and is FREE RUNNING, and will not be stopped by PCI_STP#. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/ 2 CPU frequency. SELECT 66.6/60MHz# This Input pin controls the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. If a logic "1" value is present on this pin, the 66.6 MHz Clock will be selected. If a logic "0" is used, the 60MHz frequency will be selected.
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ICS9148-12
Technical Pin Function Descriptions
MODE This Input pin is used to select the Input function of the I/O pins. An active Low will place the I/O pins in the Input mode and enable those stop clock functions. CPU3.3_2.5# This Input pin controls the CPU and IOAPIC output buffer strength for skew matching CPU and SDRAM outputs to compensate for the external VDDL supply condition. It is important to use this function when selecting power supply requirements for VDDL1,2. A logic "0" (ground) will indicate 2.5V operation and a logic "1" will indicate 3.3V operation. This pin has an internal pullup resistor to VDD. PWR_DWN# This is an asynchronous active Low Input pin used to Power Down the device into a Low Power state by not removing the power supply. The internal Clocks are disabled and the VCO and Crystal are stopped. Powered Down will also place all the Outputs in a low state at the end of their current cycle. The latency of Power Down will not be greater than 3ms. The I2C inputs will be Tri-Stated and the device will retain all programming information. This input pin only valid when MODE=0 (Power Management Mode) CPU_STOP# This is a synchronous active Low Input pin used to stop the CPUCLK clocks in an active low state. All other Clocks including SDRAM clocks will continue to run while this function is enabled. The CPUCLK's will have a turn ON latency of at least 3 CPU clocks. This input pin only valid when MODE=0 (Power Management Mode) PCI_STOP# This is a synchronous active Low Input pin used to stop the PCICLK clocks in an active low state. It will not effect PCICLK_F nor any other outputs. This input pin only valid when MODE=0 (Power Management Mode) I2C The SDATA and SCLOCK Inputs are use to program the device. The clock generator is a slave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I2C specification in Philips I2C Peripherals Data Handbook (1996) should be followed.
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ICS9148-12
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9148-12
Select Functions
Functionality Tristate Testmode
CPU HI - Z TCLK/21
PCI, PCI_F HI - Z TCLK/41
SDRAM HI - Z TCLK/21
REF HI - Z TCLK1
IOAPIC HI - Z TCLK1
24 MHz 48 MHz Selection Selection HI - Z TCLK/41 HI - Z TCLK/21
Notes: 1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0) (default on Bits 3, 2 = 1) Note: PWD = Power-Up Default
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 23 22 PIN# DESCRIPTION R e s e r ve d M u s t b e 0 fo r n o r m a l o p e ra t i on In Spread Spectr um, Controls type ( 0 = c e n t e r e d , 1 = d ow n s p r e a d ) In Spread Spectrum, Controls Spreading (0=1.8% 1=0.6%) 4 8 / 2 4 M H z ( Fr e q u e n c y S e l e c t ) 1 = 4 8 M H z , 0 = 2 4 M H z 4 8 / 2 4 M H z ( Fr e q u e n c y S e l e c t ) 1 = 4 8 M H z , 0 = 2 4 M H z Bit0 Bit1 1 - Tr i - S t a t e 1 0 - S p r e a d S p e c t r u m E n a bl e 1 1 - Te s t m o d e 0 0 - Nor mal operation 0 PWD 0 0 0 0 1 1
-
0 0
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ICS9148-12
Byte 1: CPU, 24/48 MHz Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 23 22 38 39 41 42 PWD 1 1 1 1 1 1 1 1 DESCRIPTION 48/24 MHz (Act/Inact) 48/24 MHz (Act/Inact) R e s e r ve d R e s e r ve d CPUCLK3 (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCICLK Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 8 16 14 13 12 11 9 PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d PCICLK_F (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 3: SDRAM Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 26 27 29 30 32 33 35 36 PWD 1 1 1 1 1 1 1 1 DESCRIPTION SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1(Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 5: Peripheral Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 45 1 2 PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d IOAPIC0 (Act/Inact) R e s e r ve d R e s e r ve d REF1 (Act/Inact) REF0 (Act/Inact)
Byte 6: Optional Register for Future
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for future applications.
Note: PWD = Power-Up Default
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ICS9148-12
Power Management
Clock Enable Configuration
Other Clocks, SDRAM, R E F, I OA P I C s , 48/24 MHz A 48/24 MHz B Stopped Running Running Running Running
C P U _ S TO P #
P C I _ S TO P #
P W R _ DW N #
CPUCLK
PCICLK
Crystal
VCOs
X 0 0 1 1
X 0 1 0 1
0 1 1 1 1
L ow Low Low 66.6/60 MHz 66.6/60 MHz
L ow Low 33.3/30 MHz Low 33.3/30 MHz
O ff Running Running Running Running
O ff Running Running Running Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9148-12 Power Management Requirements
SIGNAL C P U _ S TO P # P C I _ S TO P # PWR_DWN# SIGNAL STATE 0 (Disabled)2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1 1 (Normal Operation)3 0 (Power Down)4 L a t e n cy No. of rising edges of free running PCICLK 1 1 1 1 3mS 2max
Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only. The REF and IOAPIC will be stopped independant of these.
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ICS9148-12
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9148-12. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9148-12. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-12. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-12 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
(Drawing shown on next page.)
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ICS9148-12
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internal by the ICS9148-12 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don't care signals during the power down operations.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
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ICS9148-12
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time1 Clk Stabilization1 Skew1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi CIN CINX Ttrans Ts TSTAB
CONDITIONS
MIN 2 VSS - 0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq.
0.1 2.0 -100 60 400 14.318
MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 100 mA 600 mA MHz 5 45 3 3 pF pF ms ms mS ps ns
27
36
TCPU-SDRAM1 VT = 1.5 V TCPU-PCI1 VT = 1.5 V;
1.5
200 3.2
500 4.5
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current Skew1
1
SYMBOL CONDITIONS IDD2.5OP CL = 0 pF; Select @ 66M IDD2.5PD CL = 0 pF;
MIN
TYP 5 0.21 150 2.8
MAX 20 1.0 500 4
UNITS mA mA ps ns
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
1
Guaranteed by design, not 100% tested in production.
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ICS9148-12
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO2 RDSP2A1 RDSN2A1 VOH2A VOL2A I OH2A I OL2A t r2A1 t f2A1 dt2A1 t sk2A1 t j1s2A1 t jabs2A1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) I OH = -28 mA I OL = 27 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 60 10 10 2.4
TYP
MAX UNITS 66 MHz 20 20 V V mA mA ns ns % ps ps ps ps
49.3
2.5 0.35 -52 59 1.1 0.95
0.4 -48 2.85 2.85 55 250 250 150 +250
45
51 80 170 60
t jcyc-cyc2A1 VT = 1.5 V -250
100
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO2 RDSP2B1 RDSN2B1 VOH2B VOL2B I OH2B I OL2B t r2B1 t f2B1 dt2B1 t sk2B1 t jcyc-cyc2B1 t j1s2B1 t jabs2B1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) I OH = -8.0 mA I OL = 21 mA VOH = 1.8 V VOL = 0.5 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, V OL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 60 10 10 2.1
TYP
MAX UNITS 66 MHz 20 20 V V mA mA ns ns ns ps ps ps ps
33
2.15 0.3 -22 36 1.2 0.95
0.4 -18 1.5 1.3 55 250 250 150 +250
45
50 60 150 50
-250
80
Guaranteed by design, not 100% tested in production.
0123H--03/30/04
13
ICS9148-12
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 RDSN11 VOH1 VOL1 I OH1 I OL1 t r11 t f11 dt11 tsk11 t j1s11 t jabs11
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) I OH = -14.5 mA I OL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 30 12 12 2.4
TYP -
MAX UNITS 33 MHz 55 55 V V mA mA ns ns % ps ps ps
17.1
2.7 0.2 -47 47.5 1.5 1.1
0.4 -22 2 2 55 250 150 250
45
51 100 50
-250
120
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO3 RDSP31 RDSN31 VOH3 VOL3 I OH3 I OL3 Tr31 Tf31 Dt31 Tsk31 Tj1s31 Tjabs31
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) I OH = -24 mA I OL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 60 10 10 2.4
TYP
MAX UNITS 66 MHz 24 24 V V mA mA ns ns % ps ps ps
41
2.5 0.35 -47 47.5 1.45 1.2
0.4 -40 1.7 1.5 55 250 150 250
45
51 80 40
-250
-
Guaranteed by design, not 100% tested in production.
0123H--03/30/04
14
ICS9148-12
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO4 RDSP4A1 RDSN4A1 VOH4A VOL4A I OH4A I OL4A t r4A1 t f4A1 dt4A1 t j1s4A1 t jabs4A1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) I OH = -13 mA I OL = 18 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.5
TYP MAX UNITS 14.318 MHz 30 30 2.6 0.35 -29 37 1.1 1.6 0.4 -23 2 2 55 350 600 V V mA mA ns ns % ps ps
33
45 -600
51 160 -
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO4 RDSP4B1 RDSN4B1 VOH4\B VOL4B I OH4B I OL4B t r4B1 t f4B1 dt4B1 t j1s4B1 t jabs4B1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) I OH = -5.5 mA I OL = 9.0 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, V OL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 60 10 10 2.1
TYP
MAX UNITS 66 MHz 30 30 V V mA mA ns ns % ps ps
15
2.2 0.25 -17 16 1.4 1.1
0.3 -15 1.6 1.6 60 300 700
40 -700
53 130 -
Guaranteed by design, not 100% tested in production.
0123H--03/30/04
15
ICS9148-12
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO7 RDSP7 RDSN7 VOH7 VOL7 I OH7 I OL7 Tr71 Tf71 Dt71 Tj1s71 Tjabs71
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) I OH = -24 mA I OL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4
41
TYP MAX UNITS 14.318 MHz 24 24 2.5 V 0.35 0.4 V -47 -40 mA 47.5 mA 1.8 1.4 2 2 45 350 600 ns ns % ps ps
45 -600
52 150 -
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24M, 48M, REF(1:2)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Frequency Output Frequency Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter SYMBOL FO24M FO48M FOREF RDSP51 RDSN51 VOH5 VOL5 I OH5 I OL5 t r51 t f51 dt51 t j1s5A1 t j1s5B1 t jabs5A1 t jabs5B1 CONDITIONS MIN TYP MAX UNITS 24 MHz 48 MHz 14.318 MHz 60 60 2.5 0.2 -29 25 1.8 1.7 45 51 50 150 -250 -600 120 0.4 -22 4 4 55 150 350 250 600 ps V V mA mA ns ns % ps
VO = VDD*(0.5) VO = VDD*(0.5) I OH = -16 mA I OL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks
20 20 2.4
16
1
Guaranteed by design, not 100% tested in production.
0123H--03/30/04
16
ICS9148-12
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100 VARIATIONS AC MIN. .620 D NOM. .625 N MAX. .630 48
X
Ordering Information
ICS9148yFLF12-T
Example:
This table in inches
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0123H--03/30/04
17
ICS9148-12
240 mil (6.10mm)TSSOP Package
SYMBOL COMMON DIMENSIONS MIN. A A1 A2 b C D E1 e E -- 0.05 0.85 0.17 0.09 6.00 NOM. -- -- 0.90 -- -- 6.10 0.50 BSC 8.10 BSC 0.50 0 0.60 -- 0.70 8 See Variations MAX. 1.10 0.15 0.95 0.27 0.20 6.20 MIN. 12.40 13.90 VARIATIONS D NOM. 12.50 14.00 MAX 12.60 14.10 48 56 N
See Variations
Ordering Information
ICS9148yGLF12-T
Example:
L N
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP
Diminisions are in millimeters
240TSSOP_AN
Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0123H--03/30/04
18

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